NVDA, AMD, AMZN · US
Cerebras CS-4: same wafer, 2× clock, disagg rack | SemiAnalysis note
CS-4 keeps 5nm WSE-3; power/clock + 3-wafer backpack rack ~2× tok/s/user at similar BOM/wafer. 44GB SRAM unchanged—long-context needs disagg + HBM partners. See TileRT, AgentX v3, AMZN/Trainium.
Cite a section with a deep link, e.g. /en/r/sa-cerebras-cs4-2026#thesis
Snapshot
- Date
- 2026-08-19
- 晶圆/制程
- WSE-3 / 5nm
- 机架晶圆数
- 3（CS-3 为 2）
- 单架 TDP 约
- 125–135 kW
As-of 2026-09-25 (weekly refresh; equities aligned to §A. Missing series are N/A/null. Not investment advice.)
Structured research note on a SemiAnalysis piece (summary + investable mapping)—not a reprint. Defer to the original for detail.
Thesis
CS-4 keeps 5nm WSE-3; power/clock + 3-wafer backpack rack ~2× tok/s/user at similar BOM/wafer. 44GB SRAM unchanged—long-context needs disagg + HBM partners. See TileRT, AMZN/Trainium.
Analysis
Same wafer, 2× clock
CS-4 keeps WSE-3 (5nm); higher power/clock and better delivery/cooling roughly double tok/s/user per wafer; FLOPs and off-wafer I/O (~1.2→2.4 Tb/s) rise; ~44GB SRAM unchanged until next silicon.
Backpack rack (3 wafers)
Front power / rear compute; three backpacks per rack vs two on CS-3; external liquid cooling. Deploy power first, socket wafers later. Rack ~125–135 kW. Perf/W flat-to-slightly up; BOM/wafer may be similar—near 2× interactivity at similar TCO.
Networking & disagg
Field-upgradeable I/O enables Ethernet and AMD / Trainium partners for PDD/AFD; Cerebras as decode, HBM systems for capacity. Direct wafer links ~2µs—still “relatively” ultrafast vs ns-class competitors. Pipeline parallel remains default.
GPU interactivity narrative
Marketing “up to ~30× GPUs”; SA ballpark CS-4 ~4k vs CS-3 ~2k tok/s/user vs realistic Blackwell concurrency ~100s. Compare after TileRT. Long-context concurrency can require tens of systems.
Implications
| Angle | Implication | Site map |
|---|---|---|
| Cerebras / 超快推理层 | 互动性溢价与解耦 decode 角色 | 私有公司；映射 NVDA 软件反击 |
| NVIDIA GPU 软件 | TileRT 等抬高 GPU 互动性上限 | TileRT · NVDA |
| AWS / Trainium | 异质解耦与 EFA 叙事 | AMZN |
| AMD | 解耦搭档之一 | AMD · CUDA moat |
Outlook
Watch Hot Chips detail, CS-4 ship + AWS/OpenAI-class deploys, interactivity vs TileRT/Groq, Nexus/CS-5 (~2×/yr, 2027 throughput goal). AgentX v3 tests whether multi-GPU composability on agentic traces still favors GPU software stacks over wafer-scale specialty silicon.
Risks
References
- 原文（SemiAnalysis）: Cerebras's Next Generation CS-4: Fast Just Got Faster
- Cerebras 官方 CS-4 发布: Introducing Cerebras CS-4
- 对照 TileRT: Ultra-High Interactivity on NVIDIA GPUs? - TileRT InferenceX
- AgentX v3 (agentic full stack): AgentX InferenceX v3 · Open models catching up
Not investment advice. Copyright remains with SemiAnalysis / authors; this is an index note.
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